#ifndef F28P65X_NMIINTRUPT_H
#define F28P65X_NMIINTRUPT_H

#ifdef __cplusplus
extern "C" {
#endif

//---------------------------------------------------------------------------
// NMIINTRUPT Individual Register Bit Definitions:

struct NMICFG_BITS
{                      // bits description
    Uint32 NMIE  : 1;  // 0 Global NMI Enable
    Uint32 rsvd1 : 15; // 15:1 Reserved
};

union NMICFG_REG
{
    Uint32 all;
    struct NMICFG_BITS bit;
};

struct NMIFLG_BITS
{                             // bits description
    Uint32 NMIINT        : 1; // 0 NMI Interrupt Flag
    Uint32 CLOCKFAIL     : 1; // 1 Clock Fail Interrupt Flag
    Uint32 UNCERR        : 1; // 2 Flash/RAM/ROM Uncorrectable Error NMI Flag
    Uint32 REGPARITYERR  : 1; // 3 Register parity error
    Uint32 CPU1HWBISTERR : 1; // 4 HW BIST Error NMI Flag
    Uint32 rsvd1         : 1; // 5 Reserved
    Uint32 PIEVECTERR    : 1; // 6 PIE Vector Fetch Error Flag
    Uint32 SYSDBGNMI     : 1; // 7 System Debug Module NMI Flag
    Uint32 RLNMI         : 1; // 8 Reconfigurable Logic NMI Flag
    Uint32 CPU2WDRSn     : 1; // 9 CPU2 WDRSn Reset Indication Flag
    Uint32 CPU2NMIWDRSn  : 1; // 10 CPU2 NMIWDRSn Reset Indication Flag
    Uint32 rsvd2         : 1; // 11 Reserved
    Uint32 LSCMPERR      : 1; // 12 Lockstep Compare Error
    Uint32 ECATNMIn      : 1; // 13 EtherCAT NMI Flag
    Uint32 CRC_FAIL      : 1; // 14 BGCRC calculation failed.
    Uint32 SWERR         : 1; // 15 SW Error Force NMI Flag
};

union NMIFLG_REG
{
    Uint32 all;
    struct NMIFLG_BITS bit;
};

struct NMIFLGCLR_BITS
{                             // bits description
    Uint32 NMIINT        : 1; // 0 NMI Interrupt Flag Clear
    Uint32 CLOCKFAIL     : 1; // 1 Clock Fail Interrupt Flag Clear
    Uint32 UNCERR        : 1; // 2 Flash/RAM/ROM Uncorrectable Error NMI Flag Clear
    Uint32 REGPARITYERR  : 1; // 3 Register parity error Clear
    Uint32 CPU1HWBISTERR : 1; // 4 HW BIST Error NMI Flag Clear
    Uint32 rsvd1         : 1; // 5 Reserved
    Uint32 PIEVECTERR    : 1; // 6 PIE Vector Fetch Error Flag Clear
    Uint32 SYSDBGNMI     : 1; // 7 System Debug Module NMI Flag Clear
    Uint32 RLNMI         : 1; // 8 Reconfigurable Logic NMI Flag Clear
    Uint32 CPU2WDRSn     : 1; // 9 CPU2 WDRSn Reset Indication Flag Clear
    Uint32 CPU2NMIWDRSn  : 1; // 10 CPU2 NMIWDRSn Reset Indication Flag Clear
    Uint32 rsvd2         : 1; // 11 Reserved
    Uint32 LSCMPERR      : 1; // 12 Lockstep Compare Error Clear
    Uint32 ECATNMIn      : 1; // 13 EtherCAT NMI Flag Clear
    Uint32 CRC_FAIL      : 1; // 14 BGCRC calculation Flag  Clear
    Uint32 SWERR         : 1; // 15 SW Error Force NMI Flag Clear
};

union NMIFLGCLR_REG
{
    Uint32 all;
    struct NMIFLGCLR_BITS bit;
};

struct NMIFLGFRC_BITS
{                             // bits description
    Uint32 rsvd1         : 1; // 0 Reserved
    Uint32 CLOCKFAIL     : 1; // 1 Clock Fail Interrupt Flag Force
    Uint32 UNCERR        : 1; // 2 Flash/RAM/ROM Uncorrectable Error NMI Flag  Force
    Uint32 REGPARITYERR  : 1; // 3 Register parity error Force
    Uint32 CPU1HWBISTERR : 1; // 4 HW BIST Error NMI Flag  Force
    Uint32 rsvd2         : 1; // 5 Reserved
    Uint32 PIEVECTERR    : 1; // 6 PIE Vector Fetch Error Flag Force
    Uint32 SYSDBGNMI     : 1; // 7 System Debug Module NMI Flag Force
    Uint32 RLNMI         : 1; // 8 Reconfigurable Logic NMI Flag Force
    Uint32 CPU2WDRSn     : 1; // 9 CPU2 WDRSn Reset Indication Flag Force
    Uint32 CPU2NMIWDRSn  : 1; // 10 CPU2 NMIWDRSn Reset Indication Flag Force
    Uint32 rsvd3         : 1; // 11 Reserved
    Uint32 LSCMPERR      : 1; // 12 Lockstep Compare Error Force
    Uint32 ECATNMIn      : 1; // 13 EtherCAT NMI Flag Force
    Uint32 CRC_FAIL      : 1; // 14 BGCRC calculation Flag  Force
    Uint32 SWERR         : 1; // 15 SW Error Force NMI Flag Force
};

union NMIFLGFRC_REG
{
    Uint32 all;
    struct NMIFLGFRC_BITS bit;
};

struct NMISHDFLG_BITS
{                             // bits description
    Uint32 rsvd1         : 1; // 0 Reserved
    Uint32 CLOCKFAIL     : 1; // 1 Shadow Clock Fail Interrupt Flag
    Uint32 UNCERR        : 1; // 2 Shadow Flash/RAM/ROM Uncorrectable Error NMI Flag
    Uint32 REGPARITYERR  : 1; // 3 Shadow Register parity error
    Uint32 CPU1HWBISTERR : 1; // 4 Shadow HW BIST Error NMI Flag
    Uint32 rsvd2         : 1; // 5 Reserved
    Uint32 PIEVECTERR    : 1; // 6 Shadow PIE Vector Fetch Error Flag
    Uint32 SYSDBGNMI     : 1; // 7 Shadow System Debug Module NMI Flag
    Uint32 RLNMI         : 1; // 8 Shadow Reconfigurable Logic NMI Flag
    Uint32 CPU2WDRSn     : 1; // 9 Shadow CPU2 WDRSn Reset Indication Flag
    Uint32 CPU2NMIWDRSn  : 1; // 10 Shadow CPU2 NMIWDRSn Reset Indication Flag
    Uint32 rsvd3         : 1; // 11 Reserved
    Uint32 LSCMPERR      : 1; // 12 ShadowLockstep Compare Error
    Uint32 ECATNMIn      : 1; // 13 Shadow EtherCAT NMI Flag
    Uint32 CRC_FAIL      : 1; // 14 Shadow BGCRC calculation failed flag
    Uint32 SWERR         : 1; // 15 SW Error Force NMI Flag
};

union NMISHDFLG_REG
{
    Uint32 all;
    struct NMISHDFLG_BITS bit;
};

struct ERRORSTS_BITS
{                       // bits description
    Uint32 ERROR  : 1;  // 0 Error flag.
    Uint32 PINSTS : 1;  // 1 Error pin status.
    Uint32 rsvd1  : 14; // 15:2 Reserved
};

union ERRORSTS_REG
{
    Uint32 all;
    struct ERRORSTS_BITS bit;
};

struct ERRORSTSCLR_BITS
{                      // bits description
    Uint32 ERROR : 1;  // 0 ERRORFLG.ERROR clear bit
    Uint32 rsvd1 : 15; // 15:1 Reserved
};

union ERRORSTSCLR_REG
{
    Uint32 all;
    struct ERRORSTSCLR_BITS bit;
};

struct ERRORSTSFRC_BITS
{                      // bits description
    Uint32 ERROR : 1;  // 0 ERRORSTS.ERROR pin force.
    Uint32 rsvd1 : 15; // 15:1 Reserved
};

union ERRORSTSFRC_REG
{
    Uint32 all;
    struct ERRORSTSFRC_BITS bit;
};

struct ERRORCTL_BITS
{                            // bits description
    Uint32 ERRORPOLSEL : 1;  // 0 ERROR pin polarity select
    Uint32 rsvd1       : 15; // 15:1 Reserved
};

union ERRORCTL_REG
{
    Uint32 all;
    struct ERRORCTL_BITS bit;
};

struct ERRORLOCK_BITS
{                         // bits description
    Uint32 ERRORCTL : 1;  // 0 ERRORCTL Lock bit
    Uint32 rsvd1    : 15; // 15:1 Reserved
};

union ERRORLOCK_REG
{
    Uint32 all;
    struct ERRORLOCK_BITS bit;
};

struct NMI_INTRUPT_REGS
{
    union NMICFG_REG NMICFG;       // NMI Configuration Register
    union NMIFLG_REG NMIFLG;       // NMI Flag Register (SYSRsn Clear)
    union NMIFLGCLR_REG NMIFLGCLR; // NMI Flag Clear Register
    union NMIFLGFRC_REG NMIFLGFRC; // NMI Flag Force Register
    Uint32 NMIWDCNT;               // NMI Watchdog Counter Register
    Uint32 NMIWDPRD;               // NMI Watchdog Period Register
    union NMISHDFLG_REG NMISHDFLG; // NMI Shadow Flag Register
    union ERRORSTS_REG
        ERRORSTS; // Error pin status (One copy of same register, readable from both CPU1 and CPU2 )
    union ERRORSTSCLR_REG ERRORSTSCLR; // ERRORSTS clear register
    union ERRORSTSFRC_REG ERRORSTSFRC; // ERRORSTS force register
    union ERRORCTL_REG
        ERRORCTL; // Error pin control register (CPU2 can only read the register, CPU1 can R/W)
    union ERRORLOCK_REG
        ERRORLOCK; // Lock register to Error pin registers. (Available only for CPU1)
};

//---------------------------------------------------------------------------
// NMIINTRUPT External References & Function Declarations:
//
extern volatile struct NMI_INTRUPT_REGS NmiIntruptRegs;
#ifdef __cplusplus
}
#endif /* extern "C" */

#endif

//===========================================================================
// End of file.
//===========================================================================
